View AD9250-170EBZ_5134797.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

14- bit, 170 msps/250 msps, jesd204b, dual analog - to - digital converter data sheet ad9250 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change with out notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 910 6, u.s.a. tel: 781.329.4700 ? 2012 analog devices, inc. all rights reserved. technical support www.analo g.com f eatures jesd204b subclass 0 or subclass 1 coded serial digital outputs signal - to - noise ratio ( snr ) = 7 0. 6 dbfs at 185 mhz a in and 250 msps spurious - free dynamic range ( sfdr ) = 8 8 dbc at 185 mhz a in and 250 msps total power con sumption: 711 m w at 250 msps 1.8 v supply voltages integer 1 - to - 8 input clock d ivider sample rates of up to 2 50 msps if sampling frequencies of up to 4 0 0 mhz internal analog - to - digital converter ( adc ) voltage reference flexible analog input range 1 .4 v p - p to 2 .0 v p - p (1.75 v p - p no minal ) adc clock duty cycle stabilizer (dcs) 95 db channel isolation/crosstalk serial port control energy saving power - down modes u ser - configurable, built - in self - test (bist) capability applications diversity radio systems multimode digital receivers (3 g) td - scdma, wim ax , wcdma, cdma2000, gsm, edge, lte docsis 3.0 cmts upstream receive paths hfc digital reverse path receivers i/q demodulation systems smart antenna systems electronic test and measurement equipment r adar r eceivers comsec radio architecture s ied detection/jamming systems general - purpose software radios broadband data applications functional block dia gram cml, tx outputs jesd-204b interface high speed serializers pipeline 14-bit adc pipeline 14-bit adc cmos digital input/ output cmos digital input/ output fast detect control registers clock generation avdd vin+a sdio sclk fdb fda pdwn serdout1 serdout0 cs vin?a vin+b vcm vin?b sysref syncinb clk rfclk drvdd dvdd agnd dgnd drgnd cmos digital input/output ad9250 10559-001 rst figure 1. product highlights 1. integrated dual, 14 - bit, 170 msps/ 250 msps adc. 2. the configurable jesd204b output block supports up to 5 gbps per lane. 3. an on - chip , phase - locked loop ( pll) allows users to provide a single adc sampling clock; the pll multiplies the adc sampling clock to produce the corresponding jesd204b data rate clock . 4. support for an optional rf c loc k input to ease system board design. 5. proprietary differential input maintains excellent snr performance for input frequencies of up to 4 0 0 mhz. 6. operation from a single 1.8 v power supply. 7. standard serial port interface (spi) that supports various product f eatures and functions such as controlling the clock dcs , power - down, test modes, voltage reference mode, over range fast detection, and serial output configuration.
ad9250 data sheet rev. 0 | page 2 of 44 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 adc dc specifications ............................................................... 4 adc ac specifications ............................................................... 5 digital specifications ................................................................... 6 switching specifications .............................................................. 8 timing specifications .................................................................. 9 absolute max imum ratings .......................................................... 10 thermal characteristics ............................................................ 10 esd caution ................................................................................ 10 pin co nfiguration and function descriptions ........................... 11 typical performance characteristics ........................................... 13 equivalent circuits ......................................................................... 17 theory of operation ...................................................................... 18 adc architecture ...................................................................... 18 analog input considerations .................................................... 18 voltage reference ....................................................................... 19 clock input considerations ...................................................... 19 power dissipation and standb y mode ..................................... 22 digital outputs ............................................................................... 23 adc overrange and gain control .......................................... 29 a dc overrange (or) ................................................................ 29 gain switching ............................................................................ 29 dc correction ................................................................................ 31 dc corre ction bandwidth ........................................................ 31 dc correction readback .......................................................... 31 dc correction freeze ................................................................ 31 dc correction (dcc) enable bits .......................................... 31 built - in self - te st (bist ) and o utput te st .................................. 32 built - in self - te st ......................................................................... 32 serial port interface (spi) .............................................................. 33 configuration using the spi ..................................................... 33 hardware interface ..................................................................... 33 spi accessible features .............................................................. 34 memory map .................................................................................. 35 reading the memory map r egister table ............................... 35 memory map register table ..................................................... 36 memory map register description ......................................... 40 applications information .............................................................. 41 design guidelines ...................................................................... 41 outline dimensions ....................................................................... 42 ordering guide .......................................................................... 42 r evision h istory 10/1 2 revision 0: initial version
data sheet ad9250 rev. 0 | page 3 of 44 general description the ad9250 is a dual, 14 - bit adc with sampling speeds of up to 250 msps. the ad9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. the adc cores feature a multistage, differential pipelined archite cture with integrated output error correction logic. the adc cores feature wide bandwidth inputs supporting a variety of user - selectable input ranges. an integrated voltage reference eases design considerations. a duty cycle stabilizer is provided to compe nsate for variations in the adc clock duty cycle, allowing the converters to maintain excellent performance. the jesd204b high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. by defau lt, the adc output data is routed directly to the two jesd204 b serial output lane s. these outputs are at cml voltage levels. four modes support any combination of m = 1 or 2 (single or dual converters) and l = 1 or 2 (one or two lanes). for dual adc mode, data can be sent through two lanes at the maximum sampling rate of 250 m sps . h owever, if data is sent through one lane , a sampling rate of up to 1 25 m sps is supported . s ynchronization inputs ( sync inb and s ysref ) are provided . flexible power - down options allow significant power savings, when desired. programmable overrange level detection is supported for each channel via the dedicated fast detect pins. programming for setup and control are accomplished using a 3 - wire spi - compatible serial interface. the ad9250 is available in a 48 - lead lfcsp and is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent.
ad9250 data sheet rev. 0 | page 4 of 44 specifications adc dc specification s avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate fo r speed grade , vin = ?1.0 dbfs differential input, 1.75 v p - p full - scale input range , duty cycle stabilizer (dcs) enabled, l ink parameters used were m = 2 and l = 2 , unless otherwise noted. table 1 . ad9250 - 170 ad9250 - 250 parameter temperature min typ max min typ max unit resolution full 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full ?16 +16 ?16 +16 mv gain error full ?6 +2 ?6 +2.5 %fsr differential nonlinearity (dnl) full 0.75 0.75 lsb 25c 0.25 0.25 lsb integral nonlinearity (inl) 1 full 2.1 3.5 lsb 25c 1.5 1.5 lsb matching characteristic offset e rror full ?15 +15 ?15 +15 mv gain error full ?2 +3.5 ?2 +3 %fsr temperature drift offset error full 2 2 ppm/c gain error full 16 44 ppm/c input referred noise vref = 1.0 v 25c 1. 49 1.49 lsb rms analog input input span full 1.75 1.75 v p -p input capacitance 2 full 2.5 2.5 pf input resistance 3 full 20 20 k? input common - mode voltage full 0.9 0.9 v power supplies supply voltage avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v dvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply current i avdd full 233 260 255 280 ma i drvdd + i dvdd full 104 113 140 160 ma power consumption sine wave input full 607 711 mw standby power 4 full 2 80 339 mw power - down power full 9 9 mw 1 measur ed with a low input frequency, full - scale sine wave. 2 input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 input resistance refers to the effective resistance between one differential input pin and its complement. 4 standby power is measured with a dc input and the clk pin active.
data sheet ad9250 rev. 0 | page 5 of 44 adc ac specification s avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ? 1.0 dbfs differential input, 1.75 v p - p full - scale input range , link parameters used were m = 2 and l = 2, unless otherwise noted. table 2 . ad9250 - 170 ad9250 - 250 parameter 1 temperature min typ max min typ max unit signal - to - noise - ratio (snr) f in = 30 mhz 25c 72.5 72. 1 dbfs f in = 90 mhz 25c 7 2.0 71. 7 dbfs full 70.7 dbfs f in = 140 mhz 25c 71.4 71.2 db fs f in = 185 mhz 25c 70.7 70.6 dbfs full 69.3 dbfs f in = 220 mhz 25c 70.1 70.0 dbfs signal - to - noise and distortion (sinad) f in = 30 mhz 25c 71.3 70. 7 dbfs f in = 90 mhz 25c 70. 9 70.5 dbfs full 69.6 dbfs f in = 140 mhz 25c 70.3 70.0 dbfs f in = 185 mhz 25c 6 9.6 69.5 dbfs full 68.0 dbfs f in = 220 mhz 25c 6 8 . 9 68. 8 dbfs effective number of bits (enob) f in = 30 mhz 25c 11.5 11.5 bits f in = 90 mhz 25c 11.4 11.4 bits f in = 140 mhz 25c 11.3 11.3 bits f in = 185 mhz 25c 11.1 11.2 bits f in = 220 mhz 25c 10.9 11.0 bits spurious - free dynamic range (sfdr) f in = 30 mhz 25c 9 2 8 9 dbc f in = 90 mhz 25c 9 5 8 6 dbc full 7 8 dbc f in = 140 mhz 25c 9 1 8 6 dbc f in = 185 mhz 25c 8 6 8 8 dbc full 80 dbc f in = 220 mhz 25c 8 5 8 8 dbc worst second or third harmonic f in = 30 mhz 25c ? 9 2 ? 89 dbc f in = 90 mhz 25c ?9 5 ?8 7 dbc full ? 78 dbc f in = 140 mhz 25c ? 9 1 ?86 dbc f in = 185 mhz 25c ?8 6 ?8 8 dbc full ? 80 dbc f in = 220 mhz 25c ?8 5 ?88 dbc worst other (harmonic or spur) f in = 30 mhz 25c ?9 5 ?94 dbc f in = 90 mhz 25c ?94 ? 96 dbc full ? 78 dbc f in = 140 mhz 25c ?97 ?96 dbc f in = 185 mhz 25c ?9 6 ? 88 dbc full ? 80 dbc f in = 220 mhz 25c ?9 3 ?9 1 dbc
ad9250 data sheet rev. 0 | page 6 of 44 ad9250 - 170 ad9250 - 250 parameter 1 temperature min typ max min typ max unit two - tone sfdr f in = 184.12 mhz (?7 dbfs), 187.12 mhz (?7 dbfs) 25c 87 84 dbc crosstalk 2 full 95 95 db full power band width 3 25c 1000 1000 mhz 1 see the an - 835 application note , understanding high speed adc testing and e valuation , for a complete set of definitions. 2 crosstalk is measured at 100 mhz with ?1.0 dbfs on one channel and no input on the alternate channel. 3 full power b andwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 db . digital specificatio ns avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, maximum sample rate for speed grade , vin = ?1.0 dbfs differential input, 1.75 v p - p full - scale input range , dcs enabled, link parameters used were m = 2 and l = 2 , un less otherwise noted. table 3 . parameter temp erature min typ max unit differential clock inputs (clk+, clk?) input clk clock rate full 40 6 25 mhz logic compliance cmos/lvds/lvpecl internal common - mode bias full 0.9 v differential input voltage full 0.3 3. 6 v p - p input voltage range full a gnd avdd v input common - mode range full 0.9 1.4 v high level input current full 0 +60 a low level input current full ? 60 0 a input capacitance full 4 pf input resis tance full 8 10 12 k? rf clock input (rfclk) input clk clock rate full 650 1500 mhz logic compliance cmos/lvds/lvpecl internal bias full 0.9 v input voltage range full agnd avdd v input voltage level high full 1.2 avdd v low full agnd 0.6 v high level input current full 0 +150 a low level input current full ?150 0 a input capacitance full 1 pf input resistance (ac - c oupled) full 8 10 12 k? sync in input ( sync in b +/sync in b ?) logic compliance lvds internal comm on - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage range full d gnd d vdd v input common - mode range full 0.9 1.4 v high level input current full ?5 +5 a low level input current full ?5 +5 a input cap acitance full 1 pf input resistance full 12 16 20 k?
data sheet ad9250 rev. 0 | page 7 of 44 parameter temp erature min typ max unit sysref input (sysref ) logic compliance lvds internal common - mode bias full 0.9 v differential input voltage range full 0.3 3.6 v p - p input voltage range full agnd avdd v input com mon - mode range full 0.9 1.4 v high level input current full ? 5 +5 a low level input current full ? 5 +5 a input capacitance full 4 pf input resistance full 8 10 12 k? logic input ( rst , cs ) 1 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ?5 +5 a low level input current full ?10 0 ?45 a input resistance full 26 k? input capacitance full 2 pf logic input (sclk/pdwn) 2 high le vel input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full 45 100 a low level input current full ?10 +10 a input resistance full 26 k? input capacitance full 2 pf logic inputs (sdio) 2 high level input voltage full 1.22 2.1 v low level input voltage full 0 0.6 v high level input current full ? 10 1 0 a low level input current full ? 100 ? 45 a input resistance full 26 k? input capacitance full 5 pf digital outputs (serdout0/serdout1) logic compliance full cml differential output voltage (v od ) full 400 600 750 mv output offset voltage (v os ) full 0.75 drvdd/2 1.05 v digital outputs (s dio / fda/fdb) high level output volt age (v oh ) full i oh = 50 a full 1.79 v i oh = 0.5 ma full 1.75 v low level output voltage (v ol ) full i ol = 1.6 ma full 0.2 v i ol = 50 a full 0.05 v 1 pull - up. 2 pull - down.
ad9250 data sheet rev. 0 | page 8 of 44 switching specificat ions table 4 . ad9250 - 170 ad9250 - 250 parameter symbol temp erature min typ max min typ max unit clock input parameters conversion rate 1 f s full 40 170 40 250 msps sysref setup time to r ising edge c lk 2 t sysr _s full 0.75 0.75 ns sysref hold time from rising edge c lk 2 t sysr _h full 0 0 ns clk pulse width high t ch divide -by - 1 mode, dcs enabled full 2.61 2.9 3.19 1.8 2.0 2. 2 ns divide - by - 1 mode, dcs disabled full 2.76 2.9 3.05 1.9 2.0 2.1 ns divide -by - 2 mode through divide -by - 8 mode full 0.8 0.8 ns aperture delay t a full 1.0 1.0 ns aperture uncertainty (jitter) t j full 0.16 0.16 ps rms data output paramete rs data output period or unit interval (ui) full l/(20 m f s ) l/(20 m f s ) seconds data output duty cycle 25c 50 50 % data valid time 25c 0.84 0.78 ui pll lock time (t lock ) 25c 25 2 5 s wake - up time standby 25c 10 10 s adc (power - down) 3 25c 250 250 s output (power - down) 4 25c 50 50 s sync inb falling edge to f irst k .28 c haracters full 4 4 multiframe s cgs phase k.28 characters du ration full 1 1 multiframe pipeline delay jesd204b m1 , l1 mode (latency) full 36 36 cycles 5 jesd204b m1 , l2 mode (latency) full 59 59 cycles jesd204b m2 , l1 mode (latency) full 25 25 cycles jesd204b m2 , l2 mode (latency) full 36 36 cycles fast detect (latency) full 7 7 cycles data rate per lane full 3.4 5.0 5.0 gbps uncorrelated bounded high probability (ubhp) jitter full 6 8 ps random jitter a t 3.4 gbps full 2.3 ps rms a t 5.0 gbps full 1.7 ps rms output rise/fall time full 6 0 60 ps differential termination resistance 25c 100 100 ? out - of - range recovery time full 3 3 cycles 1 conversion rate is the clock rate after the divider. 2 refer to figure 3 for timing diagram. 3 wake - up time adc is defined as the time required for the adc to return to normal operation from power - down mode. 4 wake - u p time output is defined as the time required for jesd204b output to return to normal operation from power - down mode. 5 cycles refers to adc conversion rate cycles.
data sheet ad9250 rev. 0 | page 9 of 44 timing specification s table 5 . parameter test conditions /comments min typ max unit spi timing requirements (s ee figure 58 ) t ds set up time between the data and the rising edge of sclk 2 ns t dh hold time between the data and the rising edge of sclk 2 ns t clk period of the sclk 40 ns t s set up time between cs and sclk 2 ns t h hold time between cs and sclk 2 ns t hi gh minimum period that sclk should be in a logic high state 10 ns t lo w minimum period that sclk should be in a logic low state 10 ns t en_sdio time required for the sdio pin to switch from an input to an output re lative to the sclk falling edge (not shown in figures) 10 ns t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figures) 10 ns t spi_rst time required after hard or soft reset u ntil spi access is available (not shown in figures) 500 s timing diagrams n ? 36 n ? 35 n ? 34 n ? 33 n ? 1 n + 1 sample n analog input signal clk? clk+ clk? clk+ serdout1 serdout0 sample n ? 36 encoded into 2 8b/10b symbols sample n ? 35 encoded into 2 8b/10b symbols sample n ? 34 encoded into 2 8b/10b symbols 10559-002 figure 2. data output timing t refs t refh t refsrf t refhrf rfclk clk? clk+ sysref+ sysref? 10559-003 figure 3. sysref setup and hold timing
ad9250 data sheet rev. 0 | page 10 of 44 absolute maximum rat ings table 6 . parameter rating electrical avdd to agnd ? 0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v d vdd to d gnd ?0.3 v to +2.0 v vin+a/vin+b, vin?a/vin?b to agnd ?0.3 v to avdd + 0.2 v clk+, clk? to agnd ?0.3 v to avdd + 0.2 v rfclk to agnd ?0.3 v to avdd + 0.2 v vcm to agnd ?0.3 v to avdd + 0.2 v cs , pdwn to a gnd ?0.3 v to a vdd + 0.3 v sclk to agnd ?0.3 v to a vdd + 0.3 v sdio to agnd ?0.3 v to a vdd + 0.3 v rst to d gnd ?0.3 v to dvdd + 0.3 v fda, fdb to d gnd ?0.3 v to dvdd + 0.3 v serdout0+, serdout0?, ser dout 1 +, ser dout 1 ? to agnd ?0.3 v to drvdd + 0.3 v syncinb+, syncinb? to dgnd ?0.3 v to dvdd + 0.3 v sys ref +, sysref ? to a gnd ?0.3 v to a vdd + 0.3 v environmental operating temperature range (ambient) ? 40c to +85c maximum junction temperature under bias 150c storage temperature range (ambient) ? 65 c to +125c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functiona l operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal ch aracteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. this increases the reliability of the solder joints, maximizing the thermal capability of the package. table 7 . thermal resistance package type airflow velocity (m/s ec ) ja 1, 2 jc 1, 3 jb 1, 4 unit 48- lead lfcsp 7 mm 7 mm (cp - 48 - 13 ) 0 2 5 2 1 4 c/w 1.0 2 2 c/w 2. 5 20 c/w 1 per jedec 51 - 7, plus jedec 25 - 5 2s2p test board. 2 per jedec jesd51 - 2 (still air) or jedec jesd51 - 6 (moving air). 3 per mil - s td - 883, method 1012.1. 4 per jedec jesd51 - 8 (still air). typical ja is specified for a 4 - layer printed circuit board ( pcb ) with a solid ground plane. as shown in table 7 , airflow increases heat d issipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the ja . esd caution
data sheet ad9250 rev. 0 | page 11 of 44 pin configuration an d function descripti ons 1 2 3 a vdd dnc pdwn 4 cs 5 sclk 6 sdio 7 dvdd 24 dvdd 23 dgnd 22 serdout0+ 21 serdout0? 20 d r vdd 19 serdout1? 18 serdout1+ 17 dgnd 16 dvdd 15 syncinb? 14 syncinb+ 13 dvdd 44 a vdd 45 vin+b 46 vin?b 47 a vdd 48 a vdd 43 a vdd 42 vcm 41 a vdd 40 a vdd 39 vin+ a 38 vin? a 37 a vdd t o p view (not to scale) ad9250 25 dnc 26 dvdd 27 rst 28 dvdd 29 a vdd 30 sysref? 31 sysref+ 32 a vdd 33 clk+ 34 clk? 35 rfclk 36 a vdd 8 dnc 9 dnc 10 fd a 1 1 fdb 12 dvdd notes 1. dnc = do not connec t . do not connect to this pin. 2. the exposed thermal paddle on the bottom of the package provides the ground reference for drvdd and avdd. this exposed paddle must be connected to ground for proper operation. 10559-004 figure 4 . pin configuration (top view) table 8 . pin function desc riptions pin no. mnemonic type description adc power supplies 1, 5, 8, 36, 37, 40, 41, 43, 44, 47, 48 avdd supply analog power supply (1.8 v nominal). 9, 11, 13, 16 , 24, 25, 30 d vdd supply digital power supply (1.8 v nominal). 12, 28, 29, 35 dnc do not connect. 17, 23 dgnd ground reference for dvdd. 20 drvdd supply jesd204b phy serial output driver supply (1.8 v nominal). note that the drvdd power is referenced to the agnd plane. exposed paddle agnd/drgnd ground the exposed thermal paddle on the bottom of the package provides the ground reference for drvdd and avdd. this exposed paddle must be connected to ground for proper operation. adc analog 2 rfclk input adc rf clock input. 3 clk ? input adc nyquist clock input complement. 4 clk + input adc nyquist clock input true. 38 vin?a input differential analog input pin (?) for channel a. 39 vin+a input differential analog input pin (+) for channel a. 42 vcm output common - mode level bias output for analog inputs. decouple this pin to ground using a 0.1 f capacitor. 45 vin+b input differential analog input pin (+) for channel b. 46 vin?b input differential analog input pin (?) for channel b. adc fast detect outputs 26 fdb output cha nnel b fast detect indicator (cmos levels). 27 fda output channel a fast detect indicator (cmos levels). digital inputs 6 sysref+ input active low jesd204b lvds sysref input true 7 sysref? input active low jesd204b lvds sysref input complement. 1 4 syncinb+ input active low jesd204b lvds sync input true 15 syncinb? input active low jesd204b lvds sync input complement.
ad9250 data sheet rev. 0 | page 12 of 44 pin no. mnemonic type description data outputs 18 serdout1+ output lane b cml output data true. 19 serdout1? output lane b cml output data complement. 21 ser dout0? output lane a cml output data complement. 22 serdout0+ output lane a cml output data true. dut controls 10 rst input digital reset (active low). 31 sdio input/output spi serial data i/o. 32 sclk input spi serial clock. 33 cs input spi chip select (active low). 34 pdwn input power - down input (active high). the operation of this pin depends on the spi mode and can be configured as power - down or standby (see table 17 ).
data sheet ad9250 rev. 0 | page 13 of 44 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, dvdd = 1.8 v, sample rate is maximum for speed grade , dcs enabled, 1 .75 v p - p differen tial input, vin = ? 1.0 dbfs, 32 k sample, t a = 25c , l ink parameters used were m = 2 and l = 2, unless otherwise noted. 0 20 40 60 80 amplitude (dbfs) frequenc y (mhz) ?120 ?100 ?80 ?60 ?40 ?20 0 10559-005 f in : 90.1mhz f s : 170msps snr: 71.8dbfs sfdr: 91dbc figure 5. ad9250 - 170 single - tone fft with f in = 90.1 mhz 0 20 40 60 80 amplitude (dbfs) frequenc y (mhz) 10559-006 f in : 185.1mhz f s : 170msps snr: 71.6dbfs sfdr: 86dbc ?120 ?100 ?80 ?60 ?40 ?20 0 figure 6. ad9250 - 170 single - tone fft with f in = 185.1 mhz ?120 ?100 ?80 ?60 ?40 ?20 0 0 20 40 60 80 amplitude (dbfs) frequenc y (mhz) 10559-007 f in : 305.1mhz f s : 170msps snr: 69.4dbfs sfdr: 85dbc figure 7. ad9250 - 170 single - tone fft with f in = 305.1 mhz 0 20 40 60 80 100 120 ?90 ?70 ?50 ?30 ?10 snr snrfs sfdr sfdr dbc s nr / s f dr ( d b c and d b f s ) i n p u t a m p l i t ud e ( d b f s ) 10559-008 figu re 8. ad9250 - 170 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz 60 65 70 75 80 85 90 95 100 0 50 100 150 200 250 300 snr f r e q u e nc y (m h z) snr/sfdr (dbc and dbfs) sfdr 10559-009 figure 9. ad9250 - 170 single - tone snr/sfdr vs. input frequency (f in ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?10 sfdr (dbc) sfdr (dbfs) imd (dbc) imd (dbfs) s f dr /i m d ( d b c a n d d b f s ) i n p u t a m p l i t ud e ( d b f s ) 10559-010 figure 10 . ad9250 - 170 two - tone sfdr/imd vs. input amplitude (a in ) with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 170 msps
ad9250 data sheet rev. 0 | page 14 of 44 ?120 ?100 ?80 ?60 ?40 ?20 0 ?90 ?70 ?50 ?30 ?10 s f dr /i m d ( d b c a n d d b f s ) i n p u t a m p l i t ud e ( d b f s ) sfdr (dbc) sfdr (dbfs) imd (dbc) imd (dbfs) 10559-0 1 1 figure 11 . ad9250 - 170 two - tone sfdr/imd vs. input amplitude (a in ) with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 17 0 msps ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 20 40 60 80 frequenc y (mhz) 10559-012 170 msps 89.12mhz at ?7dbfs 92.12mhz at ?7dbfs sfdr: 91dbc figure 12 . ad9250 - 170 two - tone fft with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 170 msps ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 0 20 40 60 80 frequenc y (mhz) 10559-013 170 msps 184.12mhz at ?7dbfs 187.12mhz at ?7dbfs sfdr: 86dbc figure 13 . ad9250 - 170 two - tone fft with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 170 msps 70 75 80 85 90 95 100 40 90 140 sfdr_a (dbc) snrfs_a (dbfs) sfdr_b (dbc) snrfs_b (dbfs) snr/sfdr (dbc and dbfs) sample r a te (mhz) 10559-014 figure 14 . ad9250 - 170 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 136 1184 8529 47521 24220 3479 450 0 100,000 200,000 300,000 400,000 500,000 600,000 n ? 6 n ? 4 n ? 2 n n + 2 n + 4 n + 6 number of hits output code 2,096,064 total hits 1.4925 lsb rms 555924 498226 387659 281445 109722 177569 10559-015 figure 15 . ad9250 - 170 grou nded input histogram ?120 ?100 amplitude (dbfs) ?80 ?60 ?40 ?20 0 0 50 100 125 frequenc y (mhz) 10559-016 f in : 90.1mhz f s : 250msps snr: 71.8dbfs sfdr: 85dbc figure 16 . ad9250 - 250 single - tone fft with f in = 90.1 mhz
data sheet ad9250 rev. 0 | page 15 of 44 amplitude (dbfs) 0 50 100 ?120 ?100 ?80 ?60 ?40 ?20 0 frequenc y (mhz) 10559-017 f in : 185.1mhz f s : 250msps snr: 70.7dbfs sfdr: 85dbc figure 17 . ad9250 - 250 single - tone fft with f in = 185.1 mhz amplitude (dbfs) 0 50 100 ?120 ?100 ?80 ?60 ?40 ?20 0 frequenc y (mhz) 10559-018 f in : 305.1mhz f s : 250msps snr: 69.1dbfs sfdr: 82dbc figure 18 . ad9250 - 250 single - tone fft with f in = 305.1 mhz 0 20 40 60 80 100 120 ?100 ?80 ?60 ?40 ?20 0 snr (dbc) snr/sfdr (dbc and dbfs) sfdr (dbc) snr (dbfs) sfdr (dbfs) ain (dbfs) 10559-019 figure 19 . ad9250 - 250 single - tone snr/sfdr vs. input amplitude (a in ) with f in = 185.1 mhz 60 70 80 90 100 0 100 200 300 snr (dbc) sfdr (dbfs) frequenc y (mhz) snr/sfdr (dbc and dbfs) 10559-020 figure 20 . ad9250 - 250 single - tone snr/sfdr vs. input frequency (f in ) ?120 ?100 ?80 ?60 ?40 ?20 0 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbfs) sfdr (dbc) imd (dbc) ain (dbfs) sfdr/imd (dbc and dbfs) imd (dbfs) 10559-021 figure 21 . ad9250 - 250 two - tone sfdr/imd vs. input amplitude (a in ) with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 250 msps sfdr/imd (dbc and dbfs) ?120 ?100 ?80 ?60 ?40 ?20 0 ?100 ?80 ?60 ?40 ?20 0 sfdr (dbc) imd (dbc) imd (dbfs) sfdr (dbfs) input amplitude (dbfs) 10559-022 figure 22 . ad9250 - 250 two - t one sfdr/imd vs. input amplitude (a in ) with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 250 msps
ad9250 data sheet rev. 0 | page 16 of 44 amplitude (dbfs) 0 50 frequenc y (mhz) 100 ?120 ?100 ?80 ?60 ?40 ?20 0 10559-023 250msps 89.12mhz at ?7dbfs 92.12mhz at ?7dbfs sfdr: 86.4dbc figure 23 . ad9250 - 250 two - tone fft with f in1 = 89.12 mhz , f in2 = 92.12 mhz, f s = 250 msps amplitude (dbfs) frequenc y (mhz) 0 50 100 ?120 ?100 ?80 ?60 ?40 ?20 0 10559-024 250msps 184.12mhz at ?7dbfs 187.12mhz at ?7dbfs sfdr: 84dbc figure 24 . ad9250 - 250 two - tone fft with f in1 = 184.12 mhz , f in2 = 187.12 mhz, f s = 250 msps snr/sfdr (dbc and dbfs) 70 75 80 85 90 95 100 40 50 100 150 200 250 sample rate (msps) sfdr_a (dbc) sfdr_b (dbc) snr_a (dbc) snr_b (dbc) 10559-025 figure 25 . ad 9250 - 250 single - tone snr/sfdr vs. sample rate (f s ) with f in = 90.1 mhz 418 2142 10549 52008 26647 4856 913 0 100k 200k 300k 400k 500k 600k n ? 6 n ? 4 n ? 2 n n + 2 n + 4 n + 6 number of hits output code 2,095,578 total hits 1.4535 lsb rms 570587 380706 276088 163389 109133 498242 10559-026 figure 26 . ad9250 - 250 grounded input histogram
data sheet ad9250 rev. 0 | page 17 of 44 equivalent circuits v i n a v d d 10559-027 figure 27 . equivalent analog input circuit 0 . 9 v 15k ? 15k ? c l k + c l k ? a v d d a v d d a v d d 10559-028 figure 28 . equivalent clock lnput circuit bias control 10k ? rfclk interna l clock driver 0.5pf 10559-029 a v d d figure 29 . equivalent rf clock lnput circuit v c m drv d d serdoutx serdoutx 4 m a 4 m a 4 m a 4 m a r t e r m 10559-030 drv d d drv d d figure 30 . digital cml output circuit 400 ? 31k ? dv d d 10559-226 figure 31 . equivalent sdio circuit 400 ? 31k ? dv d d 10559-225 figure 32 . equivalent sclk or pdwn input circuit 400 ? 28k ? dvdd dv d d 10559-224 figure 33 . equivalent cs or rst input circuit
ad9250 data sheet rev. 0 | page 18 of 44 theory of operation the ad9250 has two analog input channels a nd two jesd204b output lane s. the signal passes through several stages before appearing at the output port(s). the dual adc design can be used for diversity reception of signals, where the adcs operate identically on the same carrier b ut from two separate antennae. the adcs can also be operated with independent analog input s. the user can sample frequencies from dc to 300 mhz using appropriate lo w - pass or band - pass filtering at the adc inputs with little los s in adc performance. operation to 400 mhz analog input is permitted but occurs at the expense of increased adc noise and distortion. a s ynchronizat i on capability is provided to allow synchroni zed timing between multiple devices. programm ing and control of the ad9250 are accomplished using a 3 - pin , spi - compatible serial interface. adc architecture the ad9250 architecture consists of a dual , front - end , sample - and - hold c ircuit, followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 14 - bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample and the remaining stages to operate on the preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution fl ash adc c onnected to a switched capacitor digital - to - analog converter (dac) and an interstage residue amplifier (mdac). the mdac magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redunda ncy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage of each channel contains a differential sampling circuit that can be ac - or dc - coupled in differential or single - ende d modes. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. analog input conside r ations the analog input to the ad9250 is a differential , switched capacitor circuit that has been designed for optimum performance while processing a differential input signal. the clock signal alternatively swi tches the input between sample mode and hold mode (see the configuration shown in figure 34 ). when the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. a shunt capacitor can be placed across the inputs to provide dynamic charging c urrents. this passive network creates a low - pass filter at the adc input; therefore, the precise values are dependent on the application. in intermediate frequency (if) undersampling applications, reduce the shunt capacitors. in combination with the drivi ng source impedance, the shunt capacitors limit the input bandwidth. refer to the an - 742 application note , frequency domain response of switched - capacitor adcs ; the an - 8 27 application note , a resonant approach to interfacing amplifiers to switched - capacitor adcs ; and the analog dialogue article, transformer - coupled front - end for wideband a/d conv erters , for more information on this subject. c p ar 1 c p ar 1 c p ar 2 c p ar 2 s s s s s s c f b c f b c s c s b i a s b i a s v i n + h v i n ? 10559-034 figure 34 . switched - capacitor input for best dynamic performance, match the source impedances driving vin+ and vin? and differentially balance the inputs. input common mode the anal og inputs of t he ad9250 are not internally dc biased. in ac - coupled applications, the user must provide this bias externally. setting the device so that v cm = 0.5 avdd (or 0.9 v) is recommended for optimum perf ormance . an on - board common - mode voltage reference is included in the design and is available from t he vcm pin. using the vcm output to set the input common mode is recommended. optimum perform ance is achieved when the common - mode voltage of th e analog inp ut is set by the vcm pin voltage (typically 0.5 avdd). d ecouple t he vcm pin to ground by using a 0.1 f capacitor, as described in the applications information section. place t his decoupling capacitor close to the pin to minimiz e the series resistance and inductance between the part and this capacitor. differential input configurations optimum performance is achieved while driving the ad9250 in a differential input configuration. for ba seband applications, the ad8138 , ada4937 - 2 , ada4938 - 2 , and ada493 0 - 2 di fferential driver s provide excellent performance and a flexible interface to the adc.
data sheet ad9250 rev. 0 | page 19 of 44 the output common - mode voltage of the ad a493 0 - 2 is easily set with the vcm pin of the ad9250 (see figure 35 ), and the driver can be configured in a sallen - key filter topology to provide band - limiting of the input signal. v i n 76 . 8 ? 120 ? 0 . 1 f 200 ? 200 ? 90 ? 0 . 1 f a v d d 33 ? 33 ? 33 ? 15 ? 15 ? 5 p f 15 p f 15 p f ad c v i n ? v i n + v c m ada 4930 - 2 10559-035 figure 35 . differential inpu t configuratio n using the ada4930 - 2 for baseband applications where snr is a key parameter, differential transformer coupling is the recommended input configuration. an example is shown in figure 36. to bia s t he analog input, the vcm voltage can be conn ected to the center tap of the secondary winding of the transformer . 2 v p -p 49 . 9 ? 0 . 1 f r 1 r 1 c 1 ad c v i n + v i n ? v c m c 2 r 2 r 3 r 2 c 2 r 3 0 . 1 f 33 ? 10559-036 figure 36 . differential transformer - coupled configuration consider t he signal characte ristics when selecting a transformer . most rf transformers saturate at frequencies below a few megahertz . e xcessive signal power can also cause core saturation , which leads to distortion. at input frequencies in the second nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true snr performance of the ad9250 . for applications where snr is a key parameter, differential double balun coupling is the recommended input config uration (see figure 37) . in this configuration, the input is ac - coupled and the vcm voltage is provided to each input thro ugh a 33 ? resistor. these resistors compensate for losses in the input baluns to provide a 50 ? impedance to the driver. adc r 1 0 . 1 f 0 . 1 f 2 v p -p v i n + v i n ? v c m c 1 c 2 r 1 r 2 r 2 0 . 1 f s 0 . 1 f c 2 33 ? 33 ? s p a p r 3 r 3 0 . 1 f 33 ? 10559-037 figure 37 . differential double balun input configuration in the double balun and transformer configuration s, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. based on these parameters , the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. table 9 displays recommended values to set the rc network for different input frequency ranges. however, these values are dependent on the input signal and bandwidth and should be used only as a starting guide. note tha t the values given in table 9 are for each r1, r2, c1, c2, and r3 component s shown in figure 36 and figure 37. table 9 . example rc network frequency range (mhz) r1 series (?) c1 differential (pf) r2 series (?) c2 shunt (pf) r3 shunt (?) 0 to 100 33 8.2 0 15 49.9 100 to 30 0 15 3.9 0 8.2 49.9 an alternative to using a transformer - coupled input at frequencies in the second nyquist zone is to use an amplifier with variab le gain. the ad8375 or ad8376 digital variable gain amplifier (dvgas) provide s good performance for driving the ad9250 . figure 38 shows an example of the ad8376 driving the ad9250 through a band - pass antialiasing filter. ad 837 6 adc 1 h 1 h 1 n f 1 n f vp o s v c m 15 p f 68 n h 2 0 k ? U2.5 p f 301 ? 165 ? 165 ? 5 . 1 p f 3 . 9 p f 180 n h 1000 p f 1000 p f n o t es 1 . a l l i ndu c t o r s ar e c oi l cra f t ? 0603 c s c o mp o n e n t s w i t h t h e ex c ep t io n o f t h e 1 h ch o k e i ndu c t o r s ( c o i l cra ft 0603 l s). 2 . f i l t er v a l u es s h o w n ar e f o r a 20 m h z band w i d t h f i l t er c e n t e r ed a t 140 m h z. 180 n h 220 n h 220 n h 10559-038 figure 38 . differential input configuration using the ad8376 voltage reference a stable and accurate voltage reference is built into the ad9250 . the full - scale input rang e can be adjusted by varying the reference voltage via the spi . the input span of the adc tracks the reference voltage changes linearly. clock input consider ations the ad9250 has two options for deriving the inp ut sampling clock, a differential nyquist sampling clock input or an rf clock input (which is internally divided by 4). the clock input is selected in register 0x09 and by default is configured for the nyquist c lock input. for optimum performance, clock th e ad9250 nyquist sample clock input, clk + and clk? , with a differential signal . the signal is typically ac - coupled into the clk+ and clk? pins via a transformer or via capacitors. these pins are biased internally (see figure 39 ) and require no external bias. i f the clock inputs are floated, clk? is pulled slightly lower than clk+ to prevent spurious clocking.
ad9250 data sheet rev. 0 | page 20 of 44 nyquist clock input options the ad9250 nyquist c lock input supports a differential clock between 40 mhz to 62 5 mhz. the clock input structure supports differential input voltages from 0.3 v to 3.6 v and is therefore compatible with various logic family inputs , such as cmos, lvds , and lvpecl. a sine wave input is also accepted, but higher slew rates typically prov ide optimal performance. clock source jitter is a critical parameter that can affect performance, as described in the jitter considerations section. if the inputs are floated, pull the clk? pin low to prevent spurious clocking. the nyquist c lock input pin s, clk+ and clk ?, are internally biased to 0.9 v and have a typical input impedance of 4 pf in parallel with 10 k ? ( see figure 39) . the input clock is typic ally ac - coupled to clk+ and clk ? . some typical clock drive circuits are presented in figure 40 through figure 43 for reference. a v d d c l k + 4 p f 4 p f c l k ? 0 . 9 v 10559-039 figure 39 . equivalent nyquist clock input circuit for application s where a single - ended low jitter clock between 40 mhz to 200 mhz is available, an rf t ransformer is recommended. an example using an rf transformer in the clock network is shown in figure 40 . at fr equencies above 200 mhz, an rf balun is recommended, as seen in figure 41 . the back - to - back schottky diodes across the transformer secondary limit clock excursions into the ad9250 to approximately 0.8 v p - p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9250 , yet preserves the fast rise and fall times o f the clock, which are critical to low jitter performance. 390 p f 390 p f 390 p f s ch o tt k y d io d es: h sms 282 2 c l o c k i n p u t 50 ? 100 ? c l k ? c l k + ad c m i n i - c i rc u i ts ? ad t 1 - 1 wt , 1 : 1 z x f mr 10559-040 figure 40 . transformer - coupled differential clock (up to 200 mhz) 390 p f 390 p f 390 p f c l o c k i n p u t 1 n f 25 ? 25 ? c l k ? c l k + s ch o tt k y d io d es: h sms 282 2 ad c 10559-041 figure 41 . balun - coupled differential clock (up to 6 25 mhz) in some cases , i t is desirable to buffer or generate multiple clock s from a single source. in those cases , analog devices , inc., offers clock drivers with excellent jitter performance. figure 42 shows a typical pecl d river circuit that u s e s pecl drivers such as the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522 , ad9523 , ad9524 , and adclk905 , adclk907 , and adclk925 . 100 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 240 ? 240 ? pe c l dr i ver 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad 95x x ad c 10559-042 figure 42 . different ial pecl sample clock (up to 6 25 mhz) analog devices also offers lvds clock drivers with excellent jitter performance. a typical circuit is shown in figure 43 and uses lvds drivers such as the ad9510 , ad9511 , ad9512 , ad9513 , ad9514 , ad9515 , ad9516 , ad9517 , ad9518 , ad9520 , ad9522 , ad9523 , and ad9524 . 1 0 0 ? 0 . 1 f 0 . 1 f 0 . 1 f 0 . 1 f 50k ? 50k ? c l k ? c l k + c l o c k i n p u t c l o c k i n p u t ad 95x x l v d s dr i ver ad c 10559-043 figure 43 . differential lvds sample clock (up to 625 mhz) rf clock input options the ad9250 rf c lock i nput support s a single - ended clock between 625 ghz to 1.5 ghz. the equivalent rf c lock input circuit is shown in figure 44 . the input is self bias ed to 0.9 v and is typically ac - coupled. the input has a typical inp ut impedance of 10 k ? in parallel with 1 pf at the rfclk pin. bias control 10k ? rfclk interna l clock driver 0.5pf 10559-044 figure 44 . equivalent rf clock input circuit it is recommended to drive the rf clock input of the ad9250 with a pecl or si ne wave signal with a minimum signal amplitude of 600 mv peak to peak. regardless of the type of signal being used, clock source jitter is of the most concern, as described in the jitter considerations section. figure 45 shows the preferred method of clocking when using the rf clock input on the ad9250 . it is recommended to u s e a 50 ? tran smission line to route the clock signal to the rf clock input of the ad9250 due to the high frequency nature of the signal and terminate the transmission line close to the rf clock input. rfclk ad c 50 ? tx line rf clock input 0.1 f 50 ? 10559-045 figure 45 . typical rf clock input circuit
data sheet ad9250 rev. 0 | page 21 of 44 0.1 f 0.1f 0.1f 0.1f lvpecl driver ad 9515 127 v dd 82.5 127 82.5 clock input clock input rfclk ad c 50 ? tx line 0.1 f 50 ? 10559-046 figure 46 . differential pecl rf clock input circuit figure 46 shows the rf clock input of the ad9250 being driven from the lvpecl outputs of the ad9515 . the differential lvpecl output signal from the ad9515 is converted to a single - ended signal usin g an rf balun or rf transformer. the rf balun configuration is recommended for clock frequencies associated with the rf clock input. input clock divider the ad9250 contains an input clock divider with the ability to divide the nyquist input clock by integer values between 1 and 8. the rf clock input uses an on - chip predivider to divide the clock input by four before it reaches the 1 to 8 divider. this allows higher input frequencies to be achieved on the rf clock input. the divide ratios can be selected using r egister 0x09 and register 0x0b. register 0x09 is used to set the rf clock input , and register 0x0b can be used to set the divide ratio of the 1 - to - 8 divider for both the rf clock input and the nyquist clock i nput. for divide ratios other than 1 , the duty - cycle stabilizer is automatically enabled. rfclk nyquist clock 1 to 8 divider 10559-047 4 figure 47 . ad9250 clock divider circuit the ad9250 clock divider can be synchronized using the external sysref input. bit 1 and bit 2 of register 0x3a allow the clock divider to be resynchronized on every sysref signal or only on the first signal after the register is written. a valid sysref causes the cl ock divider to reset to its initial state. this synchro nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a var iety of internal timing signals and , as a result , may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics . the ad9250 conta ins a dcs t hat retimes the nonsampling (falling ) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad9250 . jitter o n the rising edge of the input clock is still of paramount concern and is not reduced by the duty cycle stabilizer . the duty cycle control loop does not func tion for clock rates less than 40 mhz nominally. the loop h as a time constant associated with it that must be considered when the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. du ring the time that the loop is not locked, the dcs loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. in such applications, it may be appropriate to disable the duty cycle stabilizer. in all other applications, enabling the dcs circuit is recommended to maximize ac performance. jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f in ) due to jitter (t j ) can be calcu lated by snr hf = ?10 log[(2 f in t jrms ) 2 + 10 ) 10 /( lf snr ? ] in the equation, the rms aperture jitter represents the root - mean - square of all jitter sources, which include the clock input, the analog input signal, and the adc apert ure jitter specification. if undersampling applications are particularly sensitive to jitter, as shown in figure 48. 80 75 70 65 60 55 50 1 10 10 0 100 0 input freque nc y (mhz) s nr (dbc ) 0. 05 ps 0.2ps 0.5ps 1ps 1.5ps meas ur ed 10559-048 figure 48 . ad9250 - 250 snr v s. input frequency and jitter
ad9250 data sheet rev. 0 | page 22 of 44 treat t he clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9250 . separate the p ower supplies for the clock drivers from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or an other meth od ), retim e it by the original clock at the last step. refer to the an - 501 application note , aperture uncertainty and adc system performance , and the an - 756 application note , sampled systems and the effects of clock phase noise and jitter , for more information about jitter performance as it relates to adcs. power dissipation an d standby mode as shown in figure 49 , the power dissipate d by the ad9250 is proportional to its sample rate. the data in figure 49 w as taken using the same operating conditions as those used for the typical performance characteristics section . 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 40 90 140 190 240 total power (w) power (avdd) power (dvdd) total power encode frequency (msps) 10559-149 figure 49 . ad9250 - 250 power vs. encode rate by asserting pdwn (either through the spi port or by asserting the pdwn pin high) , the ad9250 is placed in power - d own mode . in this state, the adc typically dissipates about 9 mw. asserting the pdwn pin low returns the ad9250 t o its normal operati ng mode. low power dissipation in power - down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power - down mode and then must be recharged when returning to nor mal operation. as a result, wake - up time is related to the time spent in power - down mode , and shorter power - down cycles result in proportion ally short er wake - up times. when using the spi port interface, the user can place the adc in power - down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake - up times are required. see th e memory map register description section and the an - 877 application note , interfacing to high speed adcs via spi , for additional details.
data sheet ad9250 rev. 0 | page 23 of 44 digital outputs jesd204b transmit top level description the ad9250 digital output uses the jedec standard n o. jesd204b, serial interface for data converters . jesd204b is a protocol to link the ad9250 to a digital processing device over a serial interface of up to 5 gbps link speeds (3.5 gbps , 14- b it adc data rate). th e benefits of the jesd204b interface include a reduction in required board area for data interface routing and the enabl ing of smaller packages for converter and logic devices. the ad9250 supports single or dual lane interfaces. jesd204b overview the jesd204b data transmit block assembles the parallel data from the adc into frames and uses 8 b /10 b encoding as well as optional scrambling to form serial output data. lane synchronization is supported using special cha racters during the initial establishment of the link , and additional synchronization is embedded in the data stream thereafter. a matching external receiver is required to lock onto the serial data stream and recover the data and clock . for additional deta ils on the jesd204b interface, refer to the jesd204b standard. the ad9250 jesd204b transmit block maps the output of the two adc s over a link. a link can be configured to use either single or dual serial differen tial outputs that are called lanes. the jesd204b specification refers to a number of parameters to define the link , and these parameters must match between the jesd204b transmitter ( ad9250 output) and receiver. the jesd204b l ink is described according to the following parameters: ? s = samples transmitted/single converter/frame cycle ( ad9250 value = 1) ? m = number of converters/converter device ( ad9250 value = 2 by default, or can be set to 1 ) ? l = number of lanes/converter device ( ad9250 value = 1 or 2) ? n = converter resolution ( ad9250 value = 14) ? n = total number of bits per sample ( ad9250 value = 16) ? cf = number of control words/frame clock cycle/converter device ( ad9250 value = 0) ? cs = number of control bits/conversion sample (configurable on the ad9250 up to 2 bits) ? k = number of frames per multiframe (configurable on the ad9250 ) ? hd = high density mode ( ad9250 value = 0) ? f = octets/frame ( ad9250 value = 2 or 4, dependent upon l = 2 or 1) ? c = control bit (overrange, overflow, underflow ; a vailable on the ad9250 ) ? t = tail bit (available on the ad9250 ) ? scr = scrambler enable/disable (configurable on the ad9250 ) ? fchk = checksum for the jesd204b parameters (a utomatically calculated and stored in register map) figure 50 shows a simplified block diagram of the ad9250 jesd204b link. by default, the ad9250 is configured to use two converters and two lanes. converter a data is output to ser dout 0 +/ ser dout 0 ?, and c onverter b is output to ser dout 1 +/ ser dout 1 ? . the ad9250 allows for other configurations such as combining the outputs of both converters onto a single lane or changing the mapping of the a and b digital o utput paths. these modes are setup through a quick configuration register in the spi register map , along with additional customizable options. by default in the ad9250 , the 14 - bit converter word from each conver ter is broken into two octets (8 bits of data). bit 0 ( msb ) through bit 7 are in the first octet. the second octet contains bit 8 through bit 13 ( lsb ) and two tail bits. the tail bits can be configured as zeros, pseudo - random number sequence or control bit s indicating overrange, underrange , or v alid data conditions. the two resulting octets can be scrambled. scrambling is optional ; however, it is available to avoid spectral peaks when transmitting similar digital data patterns. the scrambler uses a self syn chronizing , polynomial - based algorithm defined by the equation 1 + x 14 + x 15 . the descrambler in the receiver should be a self - synchronizing version of the scrambler polynomial. the two octets are then encoded with an 8 b /10 b encoder. the 8b/10b encoder wo rks by taking eight bits of data (an octet) and encoding them into a 10 - bit symbol. figure 51 shows how the 14- bit data is taken from the adc, the tail bits are added, the two octets are scrambled, and how the octets a re encoded into two 10- bit symbols. figure 51 illustrates the default data format. at the data link layer, in addition to the 8b/10b encoding, the character replacement is used to allow the receiver to monitor frame al ignment. the c haracter replacement process occurs on the frame and multiframe boundaries , and implementation depends on which boundary is occurring , and if scrambling is enabled. if scrambling is disabled, the following applies. if the last scrambled octe t of the last frame of the multi frame equals the last octet of the previous frame, the transmitter replaces the last octet with the control character /a/ = /k28.3/. on other frames within the multiframe, if the last octet in the frame equals the last octet of the previous frame, the transmitter replaces the last oct et with the control character /f /= /k28.7/. if scrambling is enabled, the following applies. if the last octet of the last frame of the multiframe equals 0x7c, the transmitter replaces the last o ctet with the control character /a/ = /k28.3/. on other frames within the multiframe, if the last octet equals 0xfc, the transmitter replaces the last oct et with the control character /f / = /k28.7/. refer to jedec standard no. 204b - july 2011 for additional information about the jesd204b interface. section 5.1 covers the transport layer and data format details and section 5.2 covers scrambling and descrambling .
ad9250 data sheet rev. 0 | page 24 of 44 jesd204b synchronization details the ad9250 is a jesd2 04b subclass 1 device and establishes synchronization of the link through two control signals, sysref and sync, and typically a common device clock. sysref and sync are common to all converter devices for alignment purposes at the system level. the synchro nization process is accomplished over three phases: code group synchronization (cgs), initial lane alignment sequenc e (ilas) , and data transmission . i f scrambling is enabled, the bit s are not actually scrambled until the data transmission phase, and the cg s phase and ilas phase do not use scrambling. cgs phase in th e cgs phase, the jesd204b transmit block transmits /k28.5/ characters. the receiver (external logic device) must locate k28.5 characters in its input data stream using clock and data recover y (cd r) techniques. once a certain number of consecutive k28.5 characters have been detected on the link lanes, the receiver initiate s a sysref edge so that the ad9250 transmit data establishes a local multifra me cloc k (lmfc) internally. the sysref edge also resets any sampling edges within the adc to align sampling instances to the lmfc. this is important to maintain synchronization across multiple devices. the receiver or logic device de - assert s the sync~ signal (s yncinb ) , and the transmitter block begin s the ilas phase. ilas phase in th e ilas phase, the transmitter send s out a known pattern , and the receiver align s all lanes of the link and verif ies the parameters of the link. the ilas phase begins after sync~ h as been de - asserted (goes high). the transmit block begin s to transmit four multiframes. dummy samples are inserted between the required characters so that full multiframes are transmitted. the four multiframes include the following: ? multi f rame 1: begins w ith a n /r/ character [k28.0] and ends with an /a/ character [k28.3]. ? multi f rame 2: begins with an /r/ character followed by a /q/ [k28.4] character, followed by link configuration parameters over 14 configuration octets (see table 10) , and ends with an /a/ character. ? multi f rame 3: i s the same as multi frame 1 . ? multi f rame 4: i s the same as multi frame 1 . data transmission phase in th e data transmission phase, frame alignment is monitored with control characters. character rep lacement is used at the end of frames. character replacement in the transmitter occurs in the following instances: ? if scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame. ? i f scrambling is enable d and the last octet of the multiframe is equal to 0x7c , or the last octet of a frame is equal to 0xfc. table 10. fourteen configuration o ctets of the ilas phase no. bit 7 ( msb ) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ( lsb ) 0 did [ 7:0 ] 1 bid [ 3:0 ] 2 lid [ 4:0 ] 3 scr l [ 4:0 ] 4 f [ 7:0 ] 5 k [ 4:0 ] 6 m [ 7:0 ] 7 cs [ 1:0 ] n [ 4:0 ] 8 subclass [ 2:0 ] n [ 4:0 ] 9 jesdv [ 2:0 ] s[ 4:0 ] 10 cf [ 4:0 ] 11 r eserved , d ont c are 12 reserved, dont care 13 fchk [ 7:0 ] link setup parameters th e following demonstrate s how to configure the ad9250 jesd204b interface. the steps to configure the output include the following: 1. d isable lanes before changing configuration 2. s elect quick configuration option 3. con figure detailed options 4. check fchk, checksum of jesd204b interface parameters 5. s et additional digital output configuration options 6. r e - enable lane(s) disable l anes before changing configuration before modifying the jesd204b link parameters, disable the link and h o ld it in reset. this is accomplished by writing l ogic 1 to register 0x5f , bit[ 0 ] . select quick configuration option write to register 0x5e, the 204b quick configuration register to select the configuration options. see table 13 for configuration options and resulting jesd204b parameter values. ? 0x11 = o ne converter, one lane ? 0x12 = o ne converter, two lanes ? 0x21 = t wo converters, one lane ? 0x22 = t wo converters, two lanes
data sheet ad9250 rev. 0 | page 25 of 44 configure detailed options configure t he t ail b its and c ontrol bits . ? with n = 16 and n = 14, there are two bits available per sample for transmitting additional information over the jesd204b link. the options are tail bits or control bits. by default, tail bits of 0b00 value are used. ? tail b its are dummy bits sent over the link to complete the two octets and do not convey any information about the input signal. tail bits can be fixed zeros (default) or psuedo random numbers (reg ister 0x5f , bit[ 6 ] ). ? one or two control bits can be used instead of the tail bits through r egister 0x72 , bits[ 7:6 ] . the tail bits can be set using reg ister 0x14 , bits[ 7:5 ] . set lane identification values . ? jesd204b allows parameters to identify the d evice and l ane. these parameters are transmitted during the ilas phase , and they are accessible in the internal registers. ? there are three identification values : d evice identification (did ), b ank identification (bid ) , and l ane identification (lid ). did and bid are device specific ; therefore , they can be used for link identif ication. set n umber of frames per m ultiframe, k ? per the jesd204b specification, a multiframe is defined as a group of k successive frames, where k is between 1 and 32, and it requires that the number of octets be between 17 and 1024. the k value is set to 32 by default in reg ister 0x70 , bits [ 7 :0 ] . note that the k value is the register value plus 1. ? the k value can be changed ; however, it must comply with a few conditions. the ad9250 uses a fixed value for octets per frame [f] based on the jesd204b quick configuration setting. k must also be a multiple of 4 and conform to the following equation. 32 k c eil (17/ f ) ? the jesd204b specification also calls for the number of octets per multiframe (k f) to be between 17 and 1024. the f value is fixed through the quick configuration setting to ensure this relationship is true. table 11. jesd204b configurable identification values did value register , bits value r ange lid ( lane 0 ) 0x67 , [ 4:0 ] 0 31 lid ( lane 1 ) 0x68 , [ 4:0 ] 0 31 did 0x64 , [ 7:0 ] 0 255 bid 0x65 , [ 3:0 ] 0 15 scramble, scr . ? scrambling can be enabled or disabled by setting r egister 0x6e , bit [ 7 ] . by default, scrambling is enabled. per the jesd204b protocol, scrambling is only functional after the l ane synchronization has completed. select l ane synchronization o ptions . most of the synchronization features of the jesd 204b interface are enabled by default for typical applications. in some cases, these features can be disabled or modified as follows : ? ilas enabling is controlled in reg ister 0x5f , bits [ 3:2 ] and by default is enabled. optionally, to support some unique inst ances of the interfaces (such as nmcda - sl), the jesd204b interface can be programmed to either disable the ilas sequence or continually repeat the ilas sequence . the ad9250 has fixed values of some of the jesd20 4b interface parameters , and they are as follows: ? [n] = 14: number of bits per converter is 14, in r egister 0x72 , bits [ 4:0 ] ? [n] = 16: number of bits per sample is 16, in r egister 0x73 , bits [ 4:0 ] ? [cf] = 0: number of control words/ frame clock cycle/conve rter is 0, in r egister 0x75 , bits [ 4:0 ] ve rif y r ead only values: l anes per link (l) , octets per frame (f) , number of converters (m), and samples per converter per frame ( s ). the ad9250 calculates values for some jesd204b parameters based on other setting s , particularly the quick configuration register selection. the read only values here are available in the register map for verification. ? [l] = l anes per link can be 1 or 2, read the values from r egister 0x6e , bit [ 0 ] ? [f] = o ctets per frame can be 1, 2 , or 4, read the value from r egister 0x6f , bits [ 7 :0 ] ? [hd] = h igh d ensity mode can be 0 or 1, read the value from r egister 0x75 , bit [ 7 ] ? [m] = n umber of converters per link can be 1 or 2, read the value from register 0 x71 , bit s[ 7: 0 ] ? [s] = s amples per converter per frame can be 1 or 2, read the value from register 0x74 , bit s[ 4: 0 ]
ad9250 data sheet rev. 0 | page 26 of 44 check fchk, checksum of jesd204b interface parameters the jesd204b parameters can be verified through the checksum value [fchk] of th e jesd204b interface parameters. each lane has a fchk value associated with it. the fchk value is transmitted during the ilas secon d m ultiframe and can be read from the internal registers. the c hecksum value is the modulo 256 sum of the parameters listed i n the no. column of table 12. the c hecksum is calculated by adding the parameter fields before they are packed into the octets shown in table 12 . the fchk for the lane configuration for da ta coming out of lane 0 can be read from register 0x79 . similarly, the f chk for the lane configuration for data coming out of lane 1 can be read from r egister 0x7a. table 12. jesd204b configuration t able u sed in ilas and chksum c al culation no. bit 7 ( msb ) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ( lsb ) 0 did [ 7:0 ] 1 bid [ 3:0 ] 2 lid [ 4:0 ] 3 scr l [ 4:0 ] 4 f [ 7:0 ] 5 k [ 4:0 ] 6 m [ 7:0 ] 7 cs [ 1:0 ] n [ 4:0 ] 8 subclass [ 2:0 ] n [ 4:0 ] 9 jesdv [ 2:0 ] s[ 4:0 ] 10 cf [ 4:0 ] additiona l digital output configuration options other data format controls include the following: ? invert polarity of serial output data: register 0x60 , bit [ 1 ] ? adc d ata format ( offset binary or twos complement): register 0x14 , bits [ 1:0 ] ? options for interpreting sin gle on sysref and sync inb : register 0x3a ? option to remap converter and lane assignments, register 0x82 and register 0x83. see figure 50 for simplified block diagram. re - enable lanes after configuration after modifying the jesd2 04b link parameters, enable the link so that the synchronization process can begin. this is accomplished by writing logic 0 to register 0x5f, bit[0]. converter a converter b converter b input converter a input sysref syncinb converter b sample converter a sample ad9250 dual adc lane 0 lane 1 serdout0 serdout1 lane 1 lane 0 a a b b prima r y converter input [0] prima r y lane output [0] prima r y converter input [0] prima r y lane output [0] jesd204b lane control (m = 1, 2; l = 1, 2) lane mux (spi register mapping: 0x82,0x83) seconda r y converter input [1] seconda r y lane output [1] seconda r y converter input [1] seconda r y lane output [1] jesd204b lane control (m = 1, 2; l = 1, 2) 10559-049 figure 50 . ad9250 tran smit link simplified block diagram
data sheet ad9250 rev. 0 | page 27 of 44 8b/10b encoder/ character replacment serializer t . . . ~sync sysref vina+ vina? serdout a path adc test pattern 16-bit jesd204b test pattern 8-bit adc a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a0 octet0 octet1 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 c0 c1 s0 s1 s2 s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 e0 e1 e2 e3 e4 e5 e6 e7 e10 e11 e12 e13 e14 e15 e16 e17 e8 e9 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 e18 e19 e19 optional scrambler 1 + x 14 + x 15 jesd204b test pattern 10-bit 10559-050 figure 51 . ad9250 digital processing of jesd204b lanes table 13. ad9250 jesd204 b typical configurations jesd204b configure s etting m ( no. of c onverters) , register 0x71 , bit s [ 7: 0 ] l ( no. of lanes) , register 0x6e , bit [ 0 ] f ( octets/frame ) , register 0x6f , bits [ 7:0 ] , r ead o nly s (samples/adc/frame) , register 0x74 , bits [ 4:0 ] , r ead o n ly hd (high density mode) , register 0x75 , bit [ 7 ] , r ead o nly 0x11 1 1 2 1 0 0x12 1 2 1 1 1 0x21 2 1 4 1 0 0x22 (default) 2 2 2 1 0 data from adc frame assembler (add tail bits) optional scrambler 1 + x 14 + x 15 8b/10b encoder to receiver 10559-052 figure 52 . ad9250 adc output data path table 14. ad9250 jesd204b frame alignment monitoring and correction replacement characters scrambling lane synchronization character to be replaced last octet in multiframe replacement character off on last octet in frame repeated from previous frame no k28.7 off on last octet in frame repeated from previous frame yes k28.3 off off last octet in frame repeated from previous frame not applicable k28.7 on on last octet in frame equals d28.7 n o k28.7 on on last octet in frame equals d28.3 yes k28.3 on off last octet in frame equals d28.7 not applicable k28.7 frame and lane alignment monitoring and correction frame alignment monitoring and correction is part of the jesd204b specificati on . the 14 - bit word requires two octets to transmit all the data. the two octets (msb and lsb), where f = 2, make up a frame. during normal operating conditions , frame alignment is monitored via alignment characters, which are inserted under certain condit ions at the end of a frame. table 14 summarizes the conditions for character insertion along with the expected characters under the various operation modes. if lane synchronization is enabled, the replacement chara cter value depends on whether the octet is at the end of a frame or at the end of a multiframe. based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replacement characters.
ad9250 data sheet rev. 0 | page 28 of 44 digital outputs and timing the ad9250 has differential digital outputs that power up by default. t he driver current is derived on - chip and sets the output current at each output equal to a nominal 4 ma. each o utput presents a 100 ? dynamic internal termination to reduce unwanted reflections. place a 100 ? differential termination resistor at each receiver input to result in a nominal 3 00 mv peak - to - peak swing at the receiver (see figure 53 ). alternatively, single - ended 50 ? termination can be used. when single - ended termination is used, the termination voltage should be drvdd/2; otherwise, ac coupling capacitors can be used to terminate to any single - ended voltage. 100? or 100? differential trace pair serdoutx+ drvdd v rxcm serdoutx? v cm = rx v cm output swing = 300mv p-p 0.1f 0.1f receiver 10559-053 fi gure 53 . ac - coupled digital output termination example the ad9250 digital outputs can interface with custom asics and fpga receivers, providing superior switching performance in noisy env ironments. single point - to - point network topologies are recommended with a single di fferential 100 ? termination resistor placed as close to the receiver logic as possible. the common mode of the digital output automatically biases itself to half the supply of the receiver (that is, the common - mode voltage is 0.9 v for a receiver supply o f 1.8 v) if dc - coupled connecting is used (see figure 54 ). for receiver logic that is not within the bounds of the drvdd supply, use an ac - coupled connection. simply place a 0.1 f capacitor on each output pin and derive a 100 ? differential termination close to the receiver side. 100? 100? differentia l trace p air d r vdd v cm = d r vdd/2 output swing = 300mv p-p receiver serdoutx+ serdoutx? 10559-054 figure 54 . dc - coupled digital output termination example if there is no far - end receiver termination , or if there is poor differential trace routing, timing errors may resu lt. to avoid such timing errors, it is recommended that the trace length be less than six inches , and that the differential output traces be close together and at equal lengths. figure 55 show s an example of the d igital output (default) data eye and time interval error (tie) jitter histogram and bathtub curve for the ad9250 lane running at 5 gbps . additional spi options allow the user to further increase the output drive r voltage swing of all four outputs to drive longer trace lengths (see register 0x15 in table 17 ). t he power dissipation of the drvdd supply increases when this option is used. see the memory map section for more details. the format of the output data is twos complement by default. to change the output data format to offset binary, see the memory map section (register 0x14 in table 17). 0 ? 0 . 5 0 . 5 uls pe r i o d 1 : h i s t o g r a m 6000 7000 ?10 0 time (ps) 10 5000 4000 1000 0 2000 3000 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 ? 2 ? ?100 ?200 0 100 200 t i me ( p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? 10559 - 056 tj@ber1: b athtub hits ey e: transition bits offset: ?0.0072 uls: 8000; 999992 total: 8000.999992 0.78 ui figure 55. ad9250 digital outputs data eye, histogram and bathtub, external 100 ? terminations at 5 gbps
data sheet ad9250 rev. 0 | page 29 of 44 0 ? 0 . 5 0 . 5 uls pe r i o d 1 : h i s t o g r a m 4000 4500 ?10 0 time (ps) 10 3500 3000 1000 0 2000 2500 1500 500 1 ?16 1 ?14 1 ?12 1 ?10 1 ?8 1 ?6 1 ?4 1 ?2 1 ber 3 ? 2 ? ?250 ?150 0 50 ?50 150 250 t i me ( p s ) 400 300 200 100 0 ?100 ?300 ?400 ?200 voltage (mv) h e i g h t 1 : eye d i a g r a m 1 ? 10559 - 15 6 tj@ber1: b athtub hits 0.84 ui ey e: transition bits offset: 0 uls: 8000; 679999 total: 8000; 679999 figure 56 . ad9250 digital outputs data eye, histogram and bathtub, external 100 ? terminations at 3.4 gbps adc overrange and ga in control in receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. the standard overflow indicator provides delayed information on the state of the analog input that is of limited value in preventing clipping. therefore, it is helpful to have a programmable threshold be low full scale that allows time to reduce the gain before the clip occurs. in addition, because input signals can have significant slew rates, latency of this function is of concern. using the spi port, the user can provide a threshold above which the fd o utput is active. bit 0 of register 0x45 enables the fast detect feature. register 0x4 7 to register 0x4 a allow the user to se t the threshold level s . as long as the signal is below the selected threshold, the fd output remains low. in this mode, the magnitud e of the data is considered in the calculation of the condition, but the sign of the data is not considered. the threshold detection responds identically to positive and negative signals outside the desired range (magnitude). adc overrange (o r) the adc overrange indicator is asserted when an overrange is detected on the input of the adc. the overrange condition is determined at the output of the adc pipeline and, therefore, is subject to a latency of 36 adc clock cycles. an overrange at the in put is indicated by this bit 36 clock cycles after it occurs. gain switching the ad9250 includes circuitry that is useful in applications either where large dynamic ranges exist , or where gain ranging amplifiers are employed. this circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. one such use is to detect when an adc is about to reach full scale with a particular input condition. the result is to pr ovide an indicator that can be used to quickly insert an attenuator that prevents adc overdrive.
ad9250 data sheet rev. 0 | page 30 of 44 fast threshold detection (fda and fdb) the fd indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold register s, located in register 0x47 and register 0x48. the selected threshold register is compared with the signal magnitude at the output of the adc. the fast upper threshold detection has a latency of 7 clock cycles. the approximate upper thre shold magnitude is defined by upper threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 16 ) the fd indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. the lower threshold is programmed in the fa st detect lower threshold register s , located at register 0x49 and register 0x4a. the fast detect lower threshold register is a 1 6 - bit register that is compared with the signal magnitude at the output of the adc. this comparison is subject to the adc pipeli ne latency but is accurate in terms of converter resolution. the lower threshold magnitude is defined by lower threshold magnitude (dbfs) = 20 log ( threshold magnitude /2 16 ) the dwell time can be programmed from 1 to 65,535 sample clock cycles by placing t he desired value in the fast detect dwell time register s , located in register 0x4b and register 0x4c. the operation of the upper threshold and lower threshold registers, along with the dwell time registers , is shown in figure 57. upper threshold lower threshold fda or fdb midscale dwell time timer reset by rise above lt timer completes before signal rises above lt dwell time 10559-057 figure 57 . threshold settings for fda and fdb signals
data sheet ad9250 rev. 0 | page 31 of 44 dc c orrection because the dc offset of the adc may be significantly larger than the signal being measured, a dc correction circuit is included to null th e dc offset before measuring the power. the dc correction circuit can also be switched into the main signal path ; however, this may not be appropriate if the adc is digitizing a time - varying signal with significant dc content, such as gsm. dc correction b andwidth the dc correction circuit is a high - pass filter with a programmable bandwidth (ranging between 0.29 hz and 2.387 khz at 245.76 msps). the bandwidth is controlled by writing to the 4 - bit dc correction bandwidth select register, located at registe r 0x40, bits[5:2]. the following equation can be used to compute the bandwidth value for the dc correction circuit: dc_corr_bw = 2 ? k ?14 f clk /(2 ) where: k is the 4 - bit value programmed in bits[5:2] of register 0x40 (values between 0 and 13 are valid for k ). f clk is the ad9250 adc sample rate in hertz. dc correction readba ck the current dc correction value can be read back in register 0x41 and register 0x42 for each channel. the dc correction value is a 16- bit value that can span the entire input range of the adc. dc correction freeze setting bit 6 of register 0x40 freezes the dc correction at its current state and continues to use the last updated value as the dc correction value. clearing this bit restar ts dc correction and adds the currently calculated value to the data. dc correction (dcc) enable bits setting bit 1 of register 0x40 enables dc correction for use in the output data signal path.
ad9250 data sheet rev. 0 | page 32 of 44 built - in self - test (bist) and outp ut test the ad9250 includes built - in test features designed to enable verification of the integrity of each channel as well as facilitate board level debugging. a bist feature is included that verifies the integrity of the digital datapath of the ad9250 . various output test options are also provided to place predictable values on the outputs of the ad9250 . built - in self - test the bist is a thorough test of the digital portion of the selected ad9250 signal path. when enabled, the test runs from an internal pseudo - random noise (pn) source through the digital datapath starting at the adc block output. the bist sequence runs for 512 cycles and stops. the bist signature value for channel a and/or channel b is placed in register 0x24 and register 0x25. the outputs are connected during this test ; therefore, the pn sequence can be observed as it runs. the p n sequence can be continued from its last value or reset from the beginning, based on the value programmed in register 0x0e, bit 2. the bist signature result varies based on the channel configuration.
data sheet ad9250 rev. 0 | page 33 of 44 serial port interfac e (spi) the ad9250 spi allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the a pplication. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields. these fields are documented in the me mory map section. for detailed operational information , see the an - 877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk pin , t he sdio pin , and the cs pin (s ee table 15 ). the sclk (serial clock) pin is used to synchronize the read and write d ata presented from/to the adc. the sdio (seri al data input/output) pin is a dual - purpose pin that allows data to be sent and read from the internal adc memory map registers. the cs (chip select bar) pin is an active low control that enables or disab les the read and write cycles. table 15. seria l port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface , reads and writes. sdio serial data input/output. a dual - purpose pin that typically serves as an input or an output, depend ing on the instruction being sent and the relative position in the timing frame. cs chip select bar. an active low control that gates the read and write cycles. the falling edge of cs , in conjunction with the rising edge of sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 58 and table 5 . other modes involving the cs are available. the cs can be held low indefinitely, which permanently enables the device; this is called streaming. the cs can stall high between bytes to allow for additional external timing. when cs is tied high, spi functions are placed in a high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16 - bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and the w1 bit s. all data is composed of 8 - bit words. the first bit of each individual byte of serial data indicates whether a read or write command is issued. this allows the sdio pin to change direction from an input to an outp ut. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on - chip memory. if the instruction is a rea dback operation, performing a readback causes the sdio pin to change direction from an input to an output at the appropriate point in the serial frame. data can be sent in msb first mode or in lsb f irst mode. msb first is the default on power - up and can be changed via the spi port configuration register. for more information about this and other features, see the an - 877 application note , interfacing to high speed adcs via spi . hardware interface the pins described in table 15 comp ri se the physical interface between the user programming device and the serial port of the ad9250 . the sclk pin and the cs pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an - 812 application note , microcontroller - based serial port interface (spi) boot circuit . do not activate t he spi port during periods when the full dynamic performa nce of the converter is required. because the sclk signal, the cs signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on - board spi bus is used for oth er devices, it may be necessary to provide buffers between this bus and the ad9250 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
ad9250 data sheet rev. 0 | page 34 of 44 spi accessible f eatures table 16 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an - 877 application not e , interfacing to high speed adcs via s pi . the ad9250 part - specific features are described in the memory map register description section . table 16 . features accessible using the spi feature name description mode allows the user to set either power - down mode or standby mode clock allows the user to access the dcs via the spi offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set up outputs output phase allows the user to set the output clock polarity output delay allows the user to vary the dco delay vref allows the user to set the reference voltage don?t care don?t care don?t care don?t care sdio sclk cs t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10559-058 figure 58 . serial port interface timing diagram
data sheet ad9250 rev. 0 | page 35 of 44 m emory ma p reading the memory m ap register table each row in the memory map register table has eight bit locations. the memory map is roughly d ivided into three sections: the chip configuration registers (address 0x00 to address 0x02); the channel index and transfer registers (address 0x05 and address 0xff); and the adc functions registers, including setup, control, and te st (address 0x08 to addr ess 0x a8 ). the memory map register table (see table 17 ) documents the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal v alue given. for example, address 0x1 4 , the output mode register, has a h exadecimal default value of 0x0 1 . this means that bit 0 = 1 , and the remaining bits are 0s. this setting is the default output format value , which is twos compl e ment . for more informat ion on this function and others, see the an - 877 application note , interfacing to high speed adcs via spi . this document details the functions controlled by register 0x00 to register 0x 25 . the remaining registers, re gister 0 x3a and register 0x 59 , are documented in th e memory map register description section. open and reserved locations all address and bit locations that are not included in table 17 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x18). if the entir e address location is open (for example, address 0x13), do not write to this address location . default values after the ad9250 is reset, critical registers are loaded with default values. the default values for the registers are given in the memory map register table, table 17. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for t h e b i t . ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. transfer register map address 0x0 9, address 0x0b, address 0x14, address 0x18, and address 0x3a to address 0x4c are shadowed. writes to these addresses do n ot affect part operation until a transfer command is issued by writing 0x01 to address 0xff, setting the transfer bit. this allows these registers to be updated internally and simultaneously when the transfer bit is set. the internal update takes place whe n the transfer bit is set, and then the bit autoclears. channel - specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed to a different value for each channel. in these cases, channel address locations are i nternally duplicated for each channel. these registers and bits are designated in table 17 as local. these local registers and bits can be accessed by setting the appropriate channel a or channel b bits in regist er 0x05. if both bits are set, the subsequent write affects the registers of both channels. in a read cycle, only channel a or channel b should be set to read one of the two registers. if both bits are set during an spi read cycle, the part returns the val ue for channel a. registers and bits designated as global in table 17 affect the entire part and the channel features for which independent settings are not allowed between channels. the settings in register 0x05 d o not affect the global registers and bits.
ad9250 data sheet rev. 0 | page 36 of 44 memory map register table all address and bit locations that are not included in table 17 are not currently supported for this device. table 17 . memory map registers reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x00 global spi c onfig 0 lsb f irst soft r eset 1 1 soft r eset lsb f irst 0 0x18 0x01 chip id ad9250 8 - bit chip id is 0xb9 0xb9 read o nly 0x02 chip i nfo speed g rade 00 = 250 msps 11 = 170 msps reserved for chip die revision currently 0x0 0x00 o r 0x30 0x05 channel i ndex spi w rite t o adc b p ath spi write to adc a p ath 0x03 0x08 pdwn m odes external pdwn m ode ; 0 = pdwn is full power down ; 1 = pdwn puts device in standby jtx in s t an dby ; 0 = 204b core is unaffected in s t an dby ; 1: 204b core is powered down except for pll during standby jesd204b power modes ; 00 = normal m ode (power up) ; 01 = power - down mode : pll off, s erializer off, clocks stopped, digital held in reset ; 10 = standby m ode: pll on, s erializer off, clocks stopped, digital held in reset chip power modes ; 00 = normal mode (power up) ; 01 = power - down mode, digital data pa th clocks disabled , digital datapath held in reset; most analog paths powered off ; 10 = standby m ode; digital datapath clocks disabled , digital datapath held in reset , some analog paths powered off 0x00 0x09 global c lock r eserved clock s election: 00 = n yquist c lock 10 = rf c lock divide by 4 11 = clock off clock duty cycle stabilizer enable 0x01 dcs enabled if c lock divider enabled 0x0a pll s tatus pll locked status 204b l ink is ready read o nly 0x0b global clock divider clock divide phase rel ative to the encode clock ; 0x0 = 0 input clock cycles delayed ; 0x1 = 1 input clock cycles delayed ; 0x2 = 2 input clock cycles delayed ; .. 0x7 = 7 input clock cycles delayed clock divider ratio relative to the encode clock ; 0x00 = d ivide by 1 ; 0x01 = d ivid e by 2 ; 0x02 = d ivide by 3 ; .. 0x7 = d ivide by 8 ; u sing a clkdiv_divide_ratio > 0 (divide ratio > 1) cause s the dcs to be automatically enabled 0x00 0x0d test control reg u ser test mode cycle ; 00 = repeat pattern (u ser pattern 1, 2, 3, 4, 1, 2, 3, 4 , 1 , ) ; 10 = s ingle pattern (u ser pattern 1, 2, 3, 4, then all zeros) long psuedo random number generator reset; 0 = l ong prn enabled ; 1 = l ong prn held in reset short psuedo random number generator reset; 0 = s hort prn enabled ; 1 = s hort prn held in reset data output test generation mode; 0000 = off (normal mode ) ; 0001 = m idscale short ; 0010 = p ositive full scale ; 0011 = n egative full scale ; 0100 = alternating checker board ; 0101 = pn s equence l ong ; 0110 = pn s equence s hort ; 0111 = 1/0 word toggle ; 1000 = user test mode (use with reg ister 0x0d , b it [7 ] and u ser pattern 1, 2, 3, 4) ; 1001 to 1110 = u nused ; 1111 = ramp output 0x00 0x0e bist t est reset bist bist e nable 0x00
data sheet ad9250 rev. 0 | page 37 of 44 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x10 customer o ffset offset a djust in lsbs from +31 to ? 32 (twos complement format) ; 01 1111 = a djust output by +31 ; 01 1110 = a djust output by +30 ; 00 0001 = a djust output by +1 ; 00 0000 = a djust output by 0 [ d efault] ; 10 0001 = a djust output by ? 31 ; 10 0000 = a dju s t output by ? 32 0x00 0x14 output m ode jtx cs bits assignment (in conjunction with reg ister 0x72) 000 = {o verrange|| u nderrange, v alid} 001 = {o verrange|| u nderrange} 010 = {o verrange|| u nderrange, b lank} 011 = {blank, valid} 100 = {blank, blank} all others = { o verrange|| u nderrange, v alid} d isable output from adc invert adc data ; 0 = n ormal (default) ; 1 = i nverted digital datapath output data format select (dfs) (local) ; 00 = o ffset b inary ; 01 = twos complement 0x01 0x15 cml output adjust jesd204b cml differential output drive level adjustment ; 000 = 81% of nominal ( that is, 238 mv) ; 001 = 89% of nominal ( that is, 262 mv) ; 010 = 98% of nominal ( that is, 286 mv) ; 011 = nominal [default] ( that is, 293 mv) ; 110 = 126% of nominal ( that is, 368 mv) 0x03 0x18 adc vref main referenc e full - scale vref adjustment ; 0 1111 = internal 2.087 v p - p ; ... 0 0001 = internal 1.772 v p - p ; 0 0000 = internal 1.75 v p - p [ d efault] ; 1 1111 = internal 1.727 v p - p ; 1 0000 = internal 1.383 v p - p 0x19 user test pattern 1 l user test pattern 1 lsb ; u s e in conjunction with r egister 0x0d and register 0 x61 0x1a user test pattern 1 m user test pattern 1 msb 0x1b user test pattern 2 l user test pattern 2 lsb 0x1c user test patter n 2 m user test pattern 2 msb 0x1d user test pattern 3 l user test pattern 3 lsb 0x1e user test pattern 3 m user test pattern 3 msb 0x1f user test pattern 4 l user test pattern 4 lsb 0x20 user test pattern 4 m user test pattern 4 msb 0x21 pll low encode 00 = f or lane speeds > 2 gbps ; 01 = f or lane speeds < 2 gbps 0x24 bist misr_lsb 0x00 read only 0x25 bist misr_msb 0x00 read only
ad9250 data sheet rev. 0 | page 38 of 44 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x3a syncinb/ sysref ctrl 0 = normal mode; 1 = realign lanes on every active syncinb 0 = normal mode; 1 = realign lanes on every active sysref sysref m ode; 0 = c ontinuous reset clock dividers; 1 = s ync on next sysref rising edge only sysref enable; 0 = disabled; 1 = enabled enable syncinb buffer; 0 = buffer disabled; 1 = buffer enabled 0x00 0x40 dcc ctrl freeze dc correction ; 0 = calculate ; 1 = f reezeval dc correction bandwidth select; correction bandwidth is 2387.32 hz/reg val; there are 14 possible values ; 0000 = 2387.32 hz ; 0001 = 1193.66 hz ; 1101 = 0.29 hz enable dcc 0 x 00 0x41 dcc value lsb dc correction value[7:0] 0x42 dcc value msb dc correction value[15:8] 0x45 fast detect control pin f unction; 0 = fast detect; 1 = o verrange force fda/fdb p ins; 0 = normal function; 1 = force to value force value of fda/fdb pins if f orce pins is true, this value is output on fd p in s enable fast detect output 0x47 fd upper threshold fast detect upper threshold[7:0] 0x48 fd upper threshold fast detect upper threshold[14:8] 0x49 fd lower threshold fast detect lower threshold[7:0] 0x4a fd lower threshold fast detect lower threshold[14: 8] 0x4b fd dwell time fast detect dwell time[7:0] 0x4c fd dwell time fast detect dwell time[15:8] 0x5e 204b quick config quick configuration re gister, always reads back 0x00 ; 0x11 = m = 1, l = 1; one converter, one lane; second converter is not a utomatically powered down ; 0x12 = m = 1, l = 2; one converter, two lanes; second converter is not automatically powered down ; 0x21 = m = 2, l = 1; two converter s , one lane ; 0x22 = m = 2, l = 2; two converter s , two lanes 0x00 always reads back 0x00 0x5f 204b l ink ctrl 1 tail bits: if cs bits are not enabled ; 0 = extra bits are 0 ; 1 = extra bits are 9 - bit pn jesd204b test sample enabled reserved; s et to 1 ilas m ode ; 01 = ilas normal mode enabled ; 11 = ilas always on, test mode reserved; set to 1 power - down jesd204b l ink ; s et high while configuring l ink parameters 0x60 204b l ink ctrl 2 reserved; set to 0 reserved; set to 0 reserved; set to 0 invert logic of jesd204b bits
data sheet ad9250 rev. 0 | page 39 of 44 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x61 204b l ink ctrl 3 reserved; set to 0 reserved; set to 0 test data inje ction point ; 01 = 10 - bit data at 8b/10b output ; 10 = 8 - bit data at scrambler input jesd204b test mode patterns; 0000 = normal operation (test mode disabled) ; 0001 = alternating checker board; 0010 = 1/0 word toggle; 0011 = pn s equence pn23 ; 0100 = p n s equence pn9 ; 0101 = continuous/repeat user test mode; 0110 = single user test mode; 0111 = r eserved ; 1000 = m odified rpat test sequence, m ust be used with jtx_test_gen_sel = 01 (output of 8b/10b) ; 1100 = pn s equence pn7 ; 1101 = pn s equence pn15 ; o ther setting are unused 0x62 204b l ink ctrl 4 r eserved 0x63 204b l ink ctrl 5 r eserved 0x64 204b did config jesd204b did value 0x65 204b bid config jesd204b bid value 0x67 204b lid c onfig 1 lane 0 lid value 0x68 204b lid c onfig 2 lane 1 lid value 0x6e 204b parameters scr/l jesd204b s crambling (scr) ; 0 = d isabled ; 1 = e nabled jesd204b l anes (l) ; 0 = 1 l ane ; 1 = 2 l anes 0x6f 204b parameters f jesd204b number of octets per frame (f) ; c alculated value read only 0x70 204b parameters k jesd204b number of frames per multiframe (k) ; set value of k per jesd204b spec ifications , but also must be a multiple of 4 octets 0x71 204b parameters m jesd204b number of converters (m) ; 0 = 1 c onverter ; 1 = 2 c onverters 0x72 204 b parameters cs/n number of c ontrol bits (cs) ; 00 = n o control bits (cs = 0) ; 01 = 1 c ontrol bit (cs = 1) ; 10 = 2 c ontrol bits (cs = 2) adc converter resolution (n) , 0xd = 14 - bit c onverter (n = 14) 0x73 204b parameters s ub c lass/np jesd204b s ub class ; 0x0 = subclass 0 ; 0x1 = subclass 1 (d efault) jesd204b n value ; 0xf = n = 16 0x2f 0x74 204b parameters s reserved; set to 1 jesd204b s amples per converter frame cycle (s) ; r ead only 0x75 204b parameters hd and cf jesd204b hd value ; read o nly jesd204b control word s per frame clock cycle per link (cf) ; r ead o nly read only 0x76 204b resv1 r eserved field number 1 0x77 204b resv2 r eserved field number 2 0x79 204b chksum0 jesd204b serial checksumvalue for lane 0 0x7a 204b chksum1 je sd204b serial checksumvalue for lane 1
ad9250 data sheet rev. 0 | page 40 of 44 reg addr (hex) register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default notes 0x82 204b lane assign 1 00 = a ssign l ogical lane 0 to physical lane a [d efault] ; 01 = a ssign logical lane 0 to physical lane b reserved; set to 1 reserved; set to 0 0x02 0x83 204b lane assign 2 reserved; s et to 1 reserved; set to 1 00 = a ssign logical lane 1 to physical lane a ; 01 = a ssign logical lane 1 to physical lane b [d efault] 0x31 0x8b 204b lmfc o ffset local multiframe clock (lmfc) phase offset value; r eset value for lmfc p hase counter when s ysref is asserted ; u sed for deterministic delay applications 0x00 0xa 8 204b p re - emphasis jesd204b p re - emphasis enable option ( c onsult factory for more detail) ; s et value to 0x04 for p re - emphasis off; s et value to 0x14 for p re - emphasis on 0x04 typically not required 0xff device update ( global) transfer s ettings memory map register description for more informat ion on functions controlled in register 0x00 to register 0x 25 , see the an - 877 application note , interfacing to high speed adcs via spi .
data sheet ad9250 rev. 0 | page 41 of 44 applications information design guidelines before starting system level de sign and layout of the ad9250 , it is recommended that the designer become familiar with these guidelines, which discuss the special circuit connections and layout requirements needed for certain pins. power and ground recommendations when connecting power to the ad9250 , it is recommended that two s eparate 1.8 v power supplies be used: the power supply for avdd can be isolated and for dvdd and drvdd it can be tied together, in which case an isolation inductor of approximately 1 h is recommended. alternately, the jesd204b phy power (drvdd) and analog (av dd ) supplies can be tied together , and a separate supply can be used for the digital outputs (dvdd). the designer can employ several different decoupling capacitors to cover both high and low frequencies. locate t hese capacitors close to the point of entry at the pc board level and close to the pins of the part with minimal trace length. when using the ad9250 , a single pcb ground plane should be sufficient. with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is mandatory that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance. mate a continuous, exposed (no solder mask) copper plane on the pcb to the ad9250 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possi ble resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be filled or plugged with nonconductive epoxy. to maximize the coverage and adhesion between the adc and the pcb, overlay a silkscreen to partition the continuous plane on the pcb into several uniform sections. this provides several tie points between the adc and the pcb during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and the pcb. see the evaluation board for a pcb layout example. for detailed information about the packaging and pcb layout of chip scale packages, refer to the an - 772 application note , a design and manufacturing guide for the l ead frame chip scale package (lfcsp) . vcm decouple t he vcm pin to ground with a 0.1 f capacitor, as shown in figure 36. for optimal channel - to - channel isolation, include a 33 ? resistor between the ad9250 vcm pin and the channel a analog input network connection , as well as between the ad9250 vcm pin and the channel b analog input netwo rk connection. spi port when the full dynamic performance of the converter is required , do not activate t he spi port during periods. because the sclk, cs , and sdio signals are typically asynchronous to the adc clock, noise from these sign als can degrade converter performance . if the on - board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9250 to keep these signals from transitioning at the con verter input pins during critical sampling periods.
ad9250 data sheet rev. 0 | page 42 of 44 outline dimensions 1 0.50 bsc bot t om view top view pin 1 indic a t or 48 13 24 36 37 exposed pa d pin 1 indic a t or * 5.65 5.60 sq 5.55 0.50 0.40 0.30 se a ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.203 ref coplanarity 0.08 0.30 0.25 0.20 05-10-2012-c 7.10 7.00 sq 6.90 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.20 min * compliant to jedec standards mo-220-wkkd-2 with exception to exposed pad dimension. figure 59 . 48 - lead lead frame chip scale package [lfcsp_ w q] 7 mm 7 mm body, very very thin quad (cp - 48 - 13 ) dimensions shown in millimeters ordering gui de model 1 temperature range package description package option ad9250bcpz -170 ?40c to +85c 48- lead lead frame chip scale package [lfcsp_ w q] cp -48-13 ad9250bcpz rl7 - 170 ?40c to +85c 48- lead lead frame chip scale package [lfcsp_ w q] cp -48-13 ad9250 - 170ebz ?40c to +85c evaluation board with ad9250 - 170 ad9250bcpz -250 ?40c to +85c 48- lead lead frame chip scale package [lfcsp_ w q] cp -48-13 ad9250bcpzrl7 - 250 ?40c to +85c 48- lead lead frame chip scale package [lfcsp_ w q] cp -48-13 ad9250 - 250ebz ?40c to +85c evaluation board with ad9250 - 250 1 z = rohs compliant part.
data sheet ad9250 rev. 0 | page 43 of 44 notes
ad9250 data sheet rev. 0 | page 44 of 44 notes ? 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10559 - 0- 10/12(0)

▲Up To Search▲

Price & Availability of AD9250-170EBZ

	To Download AD9250-170EBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .